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PRELIMINARY
2 MEG x 16 1.8V ENHANCED+ BOOT BLOCK FLASH MEMORY
FLASH MEMORY
FEATURES
* 32Mb block architecture Seventy-one erasable blocks: Eight 4K-word parameter blocks Sixty-three 32K-word main memory blocks * VCC, VCCQ, VPP voltages* 1.65V (MIN), 1.95V (MAX) VCC, VCCQ 0.9V (MIN), 1.95V (MAX) VPP (in-system PROGRAM/ERASE) 12V 5% (HV) VPP tolerant (factory programming compatibility) * Random access time: 70ns @ 1.65V VCC * Low power consumption (VCC = 1.8V) Asynchronous Read < 18mA Write/Erase < 40mA (MAX) Standby < 50A (MAX) Automatic power saving feature (APS) * Enhanced write and erase suspend options ERASE-SUSPEND-to-READ PROGRAM-SUSPEND-to-READ ERASE-SUSPEND-to-PROGRAM * Dual 64-bit chip protection registers for security purposes * Cross-compatible command support Extended command set Common flash interface * PROGRAM/ERASE cycle 100,000 WRITE/ERASE cycles per block (VPP = VPP1)
*An extended voltage range of 1.65V-2.20V for Vcc and VccQ, and 0.9V-2.20V for Vpp is available upon request. A voltage range of 1.42V-1.60V for VccQ is also available upon request.
MT28F320A18
Low Voltage, Extended Temperature 0.15m Process Technology
Ball Assignment 48-Ball FBGA
1 A B C D E F
A13
2
A11
3
A8
4
VPP
5
WP#
6
A19
7
A7
8
A4
A14
A10
WE#
RP#
A18
A17
A5
A2
A15
A12
A9
A20
A6
A3
A1
A16
DQ14
DQ5
DQ11
DQ2
DQ8
CE#
A0
VCCQ
DQ15
DQ6
DQ12
DQ3
DQ9
DQ0
VSS
VSS
DQ7
DQ13
DQ4
VCC
DQ10
DQ1
OE#
Top View (Ball Down)
Note:
See page 6 for Ball Description table. See page 36 for mechanical drawing.
OPTIONS
* Timing 70ns access * Configurations 2 Meg x 16 * Boot Block Configuration Top Bottom * Package 48-ball FBGA (6 x 8 ball grid) * Temperature Range Extended (-40C to +85C)
Part Number Example:
MARKING
-70 MT28F320A18 T B FF ET
MT28F320A18FF-70 TET
2 Meg x 16, 1.8V Enhanced+ Boot Block Flash Memory MT28F320A18_3.fm - Rev. 3, Pub. 9/2002
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PRODUCTS
AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON'S PRODUCTION DATA SHEET SPECIFICATIONS.
PRELIMINARY
2 MEG x 16 1.8V ENHANCED+ BOOT BLOCK FLASH MEMORY
GENERAL DESCRIPTION
The MT28F320A18 is a nonvolatile electrically block-erasable (Flash) memory containing eight 4Kword parameter blocks and sixty-three 32K-word main blocks. The MT28F320A18 allows soft protection for blocks, as read only, by configuring soft protection registers with dedicated command sequences. For security purposes, a 128-bit chip protection register is provided. The embedded WORD WRITE and BLOCK ERASE functions are fully automated by an on-chip write state machine (WSM). An on-chip status register can be used to monitor the WSM status and to determine the progress of the PROGRAM/ERASE task. The ERASE/PROGRAM SUSPEND functionality allows compatibility with existing EEPROM emulation software packages. The device is manufactured using 0.15m process technology. Please refer to Micron's Web site (www.micron.com/ flash) for the latest data sheet.
ARCHITECTURE AND MEMORY ORGANIZATION
The MT28F320A18 contains eight 4K-word parameter blocks and sixty-three 32K-word main blocks. Figure 2 and Figure 3 show the bottom and top memory organizations for the 32Mb device.
DEVICE MARKING
Due to the size of the package, Micron's standard part number is not printed on the top of each device. Instead, an abbreviated device mark comprised of a five-digit alphanumeric code is used. The abbreviated device marks are cross referenced to Micron part numbers in Table 1.
Table 1:
Cross Reference for Abbreviated Device Marks
PRODUCT MARKING FW722 FW723 SAMPLE MARKING FX722 FX723 MECHANICAL SAMPLE MARKING FY722 FY723
PART NUMBER MT28F320A18FF-70 BET MT28F320A18FF-70 TET
2 Meg x 16, 1.8V Enhanced+ Boot Block Flash Memory MT28F320A18_3.fm - Rev. 3, Pub. 9/2002
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PRELIMINARY
2 MEG x 16 1.8V ENHANCED+ BOOT BLOCK FLASH MEMORY
Functional Block Diagram
DQ0-DQ15 X DEC Data Input Buffer Data Register ID Reg. RP# CE# WE# OE# Y/Z DEC Bank a Blocks Y/Z Gating/Sensing
CSM
Status Reg.
WSM
Program/ Erase Change Pump Voltage Switch Output Multiplexer
DQ0-DQ15
I/O Logic
Output Buffer
A0-A20
Address Input Buffer
APS Control Address CNT WSM Address Multiplexer
Data Comparator
Y/Z DEC X DEC
Y/Z Gating/Sensing Bank b Blocks
Address Latch
2 Meg x 16, 1.8V Enhanced+ Boot Block Flash Memory MT28F320A18_3.fm - Rev. 3, Pub. 9/2002
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PRELIMINARY
2 MEG x 16 1.8V ENHANCED+ BOOT BLOCK FLASH MEMORY
PART NUMBERING INFORMATION
Micron's low-power devices are available with several different combinations of features (see Figure 1). Valid combinations of features and their corresponding part numbers are listed in Table 2.
Figure 1: Part Number Chart
MT 28F 320 A18 FF -70 T ET
Micron Technology Flash Family
28F = Dual-Supply Flash
Operating Temperature Range
ET = Extended (-40C to +85C)
Boot Block Starting Address
B = Bottom boot T = Top boot
Density/Organization/Banks
320 = 32Mb (2,048K x 16)
Access Time
-70 = 70ns
Read Mode Operation
A = Asynchronous
Package Code
FF = 48-ball FBGA (8 x 6 grid)
Operating Voltage Range
18 = 1.65V-1.95V
Table 2:
Valid Part Number Combinations
ACCESS TIME (ns) 70 70 BOOT BLOCK STARTING ADDRESS Bottom Top OPERATING TEMPERATURE RANGE -40C to +85C -40C to +85C
PART NUMBER MT28F320A18FF-70 BET MT28F320A18FF-70 TET
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PRELIMINARY
2 MEG x 16 1.8V ENHANCED+ BOOT BLOCK FLASH MEMORY
Figure 2: 32Mb Bottom Boot Block Memory Address Map
ADDRESS RANGE 1FFFFFh 1F8000h 1F7FFFh 1F0000h 1EFFFFh 1E8000h 1E7FFFh 1E0000h 1DFFFFh 1D8000h 1D7FFFh 1D0000h 1CFFFFh 1C8000h 1C7FFFh 1C0000h 1BFFFFh 1B8000h 1B7FFFh 1B0000h 1AFFFFh 1A8000h 1A7FFFh 1A0000h 19FFFFh 198000h 197FFFh 190000h 18FFFFh 188000h 187FFFh 180000h 17FFFFh 178000h 177FFFh 170000h 16FFFFh 168000h 167FFFh 160000h 15FFFFh 158000h 157FFFh 150000h 14FFFFh 148000h 147FFFh 140000h 13FFFFh 138000h 137FFFh 130000h 12FFFFh 128000h 127FFFh 120000h 11FFFFh 118000h 117FFFh 110000h 10FFFFh 108000h 107FFFh 100000h 0FFFFFh 0F8000h 0F7FFFh 0F0000h 0EFFFFh 0E8000h 0E7FFFh 0E0000h 0DFFFFh 0D8000h 0D7FFFh 0D0000h 0CFFFFh 0C8000h 0C7FFFh 0C0000h 0BFFFFh 0B8000h 0B7FFFh 0B0000h 0AFFFFh 0A8000h 0A7FFFh 0A0000h 09FFFFh 098000h 097FFFh 090000h 08FFFFh 088000h 087FFFh 080000h 07FFFFh 078000h 077FFFh 070000h 06FFFFh 068000h 067FFFh 060000h 05FFFFh 058000h 057FFFh 050000h 04FFFFh 048000h 047FFFh 040000h 03FFFFh 038000h 037FFFh 030000h 02FFFFh 028000h 027FFFh 020000h 01FFFFh 018000h 017FFFh 010000h 00FFFFh 008000h 007FFFh 000000h
Figure 3: 32Mb Top Boot Block Memory Address Map
ADDRESS RANGE 1FFFFFh 1F8000h 1F7FFFh 1F0000h 1EFFFFh 1E8000h 1E7FFFh 1E0000h 1DFFFFh 1D8000h 1D7FFFh 1D0000h 1CFFFFh 1C8000h 1C7FFFh 1C0000h 1BFFFFh 1B8000h 1B7FFFh 1B0000h 1AFFFFh 1A8000h 1A7FFFh 1A0000h 19FFFFh 198000h 197FFFh 190000h 18FFFFh 188000h 187FFFh 180000h 17FFFFh 178000h 177FFFh 170000h 16FFFFh 168000h 167FFFh 160000h 15FFFFh 158000h 157FFFh 150000h 14FFFFh 148000h 147FFFh 140000h 13FFFFh 138000h 137FFFh 130000h 12FFFFh 128000h 127FFFh 120000h 11FFFFh 118000h 117FFFh 110000h 10FFFFh 108000h 107FFFh 100000h 0FFFFFh 0F8000h 0F7FFFh 0F0000h 0EFFFFh 0E8000h 0E7FFFh 0E0000h 0DFFFFh 0D8000h 0D7FFFh 0D0000h 0CFFFFh 0C8000h 0C7FFFh 0C0000h 0BFFFFh 0B8000h 0B7FFFh 0B0000h 0AFFFFh 0A8000h 0A7FFFh 0A0000h 09FFFFh 098000h 097FFFh 090000h 08FFFFh 088000h 087FFFh 080000h 07FFFFh 078000h 077FFFh 070000h 06FFFFh 068000h 067FFFh 060000h 05FFFFh 058000h 057FFFh 050000h 04FFFFh 048000h 047FFFh 040000h 03FFFFh 038000h 037FFFh 030000h 02FFFFh 028000h 027FFFh 020000h 01FFFFh 018000h 017FFFh 010000h 00FFFFh 008000h 007FFFh 000000h
32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Blocks 8 x 4K-Word Blocks
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 007FFFh 007000h 006FFFh 006000h 005FFFh 004FFFh 004000h 003FFFh 003000h 002FFFh 002000h 001FFFh 001000h 000FFFh 000000h
8 x 4K-Word Blocks 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63
Parameter Blocks
4K-Word Block 0 1FF000h 4K-Word Block 1 1FE000h 4K-Word Block 2 1FD000h 4K-Word Block 3 1FC000h 4K-Word Block 4 1FB000h 4K-Word Block 5 1FA000h 4K-Word Block 6 1F9000h 4K-Word Block 7 1F8000h
1F8FFFh 1F9FFFh 1FAFFFh 1FBFFFh 1FCFFFh 1FDFFFh 1FEFFFh
1FFFFFh
4K-Word Block 7 4K-Word Block 6
4K-Word Block 5 005000h 4K-Word Block 4 4K-Word Block 3 4K-Word Block 2 Parameter Blocks 4K-Word Block 1 4K-Word Block 0
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PRELIMINARY
2 MEG x 16 1.8V ENHANCED+ BOOT BLOCK FLASH MEMORY
BALL DESCRIPTIONS
48-BALL FBGA NUMBERS D8, C8, B8, A8, C7, B7, A7, C6, B6, A6, C5, B5, C3, A3, C2, B2, A2, D1, C1, B1, A1 D7 F8 B3 B4 SYMBOL A0-A20 TYPE Input DESCRIPTION Address Inputs: Inputs for the address during READ and WRITE operations. Addresses are internally latched during WRITE and ERASE cycles.
CE# OE# WE# RP#
A5 E7, F7, D5, E5, F4, D3, E3, F2, D6, E6, F6, D4, E4, F3, D2, E2 A4
WP# DQ0-DQ15
Chip Enable: Activates the device when LOW. When CE# is HIGH, the device is disabled and goes into standby power mode. Input Output Enable: Enables the outputs buffer when LOW. When OE# is HIGH, the output buffers are disabled. Input Write Enable: Determines if a given cycle is a WRITE cycle. If WE# is LOW, the cycle is either a WRITE to the command state machine (CSM) or to the memory array. Input Reset: When RP# is a logic LOW, the device is in reset mode, which drives the outputs to High-Z and resets the write state machine (WSM). When RP# is at logic HIGH, the device is in standard operation. When RP# transitions from logic LOW to logic HIGH, the device resets all blocks to locked and defaults to the read array mode. Input Write Protect: Controls the lock down function of the flexible locking feature. Input/ Data Inputs/Outputs: Inputs array data on the second CE# and WE# cycle during Output PROGRAM command. Inputs commands to the command user interface when CE# and WE# are active. Supply Block Erase and Program Power Supply: [VPP1 = 0.9V-1.95V or VPP2 = 11.4V- 12.6V]. A valid voltage on this contact allows block erase or data programming. Memory contents cannot be altered when VPP VPPLK. Block erase and program at invalid VPP voltages should not be attempted. It provides factory programming compatibility when driven to 11.4V-12.6V Device Power Supply: [1.65V-1.95V] Supplies power for device operation. I/O Power Supply: [1.65V-1.95V] Supplies power for input/output buffers. This input should be tied directly to VCC. Do not float any ground ball. Internally not connected.
Input
VPP
F5 E1 E8, F1 C4
VCC VCCQ VSS NC
Supply Supply Supply -
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PRELIMINARY
2 MEG x 16 1.8V ENHANCED+ BOOT BLOCK FLASH MEMORY
COMMAND STATE MACHINE
Commands are issued to the command state machine (CSM) using standard microprocessor write timings. The CSM acts as an interface between external microprocessors and the internal write state machine (WSM). The available commands are listed in Table 3, their definitions are given in Table 4 and their descriptions in Table 5. Program and erase algorithms are automated by an on-chip WSM. Table 6 shows the CSM transition states. Once a valid PROGRAM/ERASE command is entered, the WSM executes the appropriate algorithm, which generates the necessary timing signals to control the device internally and accomplish the requested operation. A command is valid only if the exact sequence of WRITE cycles is completed. After the WSM completes its task, the WSM status bit (SR7) (see Table 8) is set to a logic HIGH level (1), allowing the CSM to respond to the full command set again. RP# must be at logic HIGH (VIH). The second operation, when needed, can be a WRITE or a READ depending upon the command. During a READ operation, control signals CE# and OE# must be at a logic LOW level (Vil), and WE# and RP# must be at logic HIGH (VIH). Table 7 illustrates the bus operations for all the modes: write, read, reset, standby, and output disable. When the device is powered up, internal reset circuitry initializes the chip to a read array mode of operation. Changing the mode of operation requires that a command code be entered into the CSM. An on-chip status register is available. The status register allows the monitoring of the progress of various operations that can take place on a memory. The status register is interrogated by entering a READ STATUS REGISTER command onto the CSM (cycle 1) and reading the register data on I/Os DQ0-DQ7 (cycle 2). Status register bits SR0-SR7 correspond to DQ0-DQ7 (see Table 8).
OPERATIONS
Device operations are selected by entering a standard JEDEC 8-bit command code with conventional microprocessor timings into an on-chip CSM through I/Os DQ0-DQ7. The number of bus cycles required to activate a command is typically one or two. The first operation is always a WRITE. Control signals CE# and WE# must be at a logic LOW level (VIL), and OE# and
Command Definition
Once a specific command code has been entered, the WSM executes an internal algorithm, generating the necessary timing signals to program, erase, and verify data. See Table 4 for the CSM command definitions and data for each of the bus cycles.
Table 3:
Command State Machine Codes For Device Mode Selection
CODE ON DEVICE MODE Program setup/alternate program setup Block erase setup Clear status register Protection configuration setup Read status register Read protection configuration register Read query Program/erase suspend Protection register program/lock Program/erase resume - erase confirm Read array
COMMAND DQ0-DQ7 40h/10h 20h 50h 60h 70h 90h 98h B0h C0h D0h FFh
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PRELIMINARY
2 MEG x 16 1.8V ENHANCED+ BOOT BLOCK FLASH MEMORY
STATUS REGISTER
The status register allows the user to determine whether the state of a PROGRAM/ERASE operation is pending or complete. The status register is monitored by toggling OE# and CE# by reading the resulting status code on I/Os DQ0-DQ7. The high-order I/Os (DQ8-DQ15) are set to 00h internally, so only the loworder I/Os (DQ0-DQ7) need to be interpreted. Register data is updated and latched on the falling edge of OE# or CE#, whichever occurs last. Latching the data prevents errors from occurring if the register input changes during a status register read. The status register provides the internal state of the WSM to the external microprocessor. During periods when the WSM is active, the status register can be polled to determine the WSM status. Table 8 defines the status register bits. After monitoring the status register during a PROGRAM/ERASE operation, the data appearing on DQ0- DQ7 remains as status register data until a new command is issued to the CSM. To return the device to other modes of operation, a new command must be issued to the CSM. CSM responds to an ERASE SUSPEND command only. When the WSM has completed its task, the WSM status bit (SR7) is set to a logic HIGH level and the CSM responds to the full command set. The CSM stays in the current command state until the microprocessor issues another command. The WSM successfully initiates an ERASE or PROGRAM operation only when VPP is within its correct voltage range.
CLEAR STATUS REGISTER
The internal circuitry can set, but not clear, the block lock status bit (SR1), the VPP status bit (SR3), the program status bit (SR4), and the erase status bit (SR5) of the status register. The CLEAR STATUS REGISTER command (50h) allows the external microprocessor to clear these status bits and synchronize to the internal operations. When the status bits are cleared, a READ ARRAY command (FFh) must be issued before data can be read from the memory array, or a READ STATUS REGISTER command (70h) must be issued to read status.
COMMAND STATE MACHINE OPERATIONS
The CSM decodes instructions for read array, read protection configuration register, read query, read status register, clear status register, program, erase, erase suspend, erase resume, erase confirm, program setup, alternate program setup, program suspend, program resume, lock block, unlock block and lock down block, chip protection register program, and chip protection register lock. The 8-bit command code is input to the device on DQ0-DQ7 (see Table 3 for CSM codes and Table 4 for command definitions). During a PROGRAM or ERASE cycle, the CSM informs the WSM that a PROGRAM or ERASE cycle has been requested. During a PROGRAM cycle, the WSM controls the program sequences and the CSM responds to a PROGRAM SUSPEND command only. During an ERASE cycle, the
READ OPERATIONS
The following READ operations are available: READ ARRAY, READ PROTECTION CONFIGURATION REGISTER, READ QUERY and READ STATUS REGISTER.
Read Array
The array is read by entering the command code FFh on DQ0-DQ7. Control signals CE# and OE# must be at a logic LOW level (VIL), and WE# and RP# must be at logic HIGH level (VIH) to read data from the array. Data is available on DQ0-DQ15. Any valid address within any of the blocks selects that address and allows data to be read from that address. Upon initial powerup or device reset, the device defaults to the read array mode.
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PRELIMINARY
2 MEG x 16 1.8V ENHANCED+ BOOT BLOCK FLASH MEMORY
Read Chip Protection Configuration Register
The chip identification mode outputs four types of information: the manufacturer/device identifier, the block locking status, the protection register content, and protection register lock. Two bus cycles are required for this operation: the chip identification data is read by entering the command code 90h on DQ0- DQ7 and the identification code address on the address lines. Control signals CE# and OE# must be at a logic LOW level (VIL), and WE# and RP# must be at a logic HIGH level (VIH) to read data from the protection configuration register. Data is available on DQ0-DQ15. To return to read array mode, write the read array command code FFh on DQ0-DQ7. See Table 10 for further details.
Table 4:
COMMAND
Command Definitions
FIRST BUS CYCLE OPERATION WRITE WRITE WRITE WRITE WRITE WRITE WRITE WRITE WRITE WRITE WRITE WRITE WRITE WRITE ADDRESS X X X X X X X X X X X X X X DATA FFh 90h 70h 50h 98h 20h 40h/10h B0h D0h 60h 60h 60h C0h C0h SECOND BUS CYCLE OPERATION READ READ READ - READ WRITE WRITE - - WRITE WRITE WRITE WRITE WRITE ADDRESS WA IA - - QA BA WA - - BA BA BA PA LPA DATA AD ID SRD - QD D0h WD - - 01h D0h 2Fh PD FFFDh
READ ARRAY READ PROTECTION CONFIGURATION REGISTER READ STATUS REGISTER CLEAR STATUS REGISTER READ QUERY BLOCK ERASE SETUP PROGRAM SETUP/ALTERNATE PROGRAM SETUP PROGRAM/ERASE SUSPEND PROGRAM/ERASE RESUME - ERASE CONFIRM LOCK BLOCK UNLOCK BLOCK LOCK DOWN BLOCK PROTECTION REGISTER PROGRAM SETUP PROTECTION REGISTER LOCK WA: IA: BA: ID: SRD: QA: QD: WD: PA: LPA: AD: PD: X:
Word address of memory location to be written, or read Identification code address Address within the block Identification code data Data read from the status register Query code address Query code data Data to be written at the location WA Protection register address Lock protection register address Array data Protection register data "Don't Care"
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2 MEG x 16 1.8V ENHANCED+ BOOT BLOCK FLASH MEMORY
Table 5:
CODE 10h 20h
Command Descriptions
DEVICE MODE BUS CYCLE First First DESCRIPTION Operates the same as a PROGRAM SETUP command. Prepares the CSM for an ERASE CONFIRM command. If the next command is not an ERASE CONFIRM command, the command will be ignored, and the device will go to read status mode and wait for another command. A two-cycle command: The first cycle prepares for a PROGRAM operation, the second cycle latches addresses and data and initiates the WSM to execute the program algorithm. The Flash device outputs status register data on the falling edge of OE# or CE#, whichever occurs first. The WSM can set the block lock status (SR1), VPP Status (SR3), program status (SR4),and erase status (SR5) bits in the status register to "1," but it cannot clear them to "0." Issuing this command clears those bits to "0." Prepares the CSM for changes to the block locking status. If the next command is not BLOCK UNLOCK, BLOCK LOCK, or BLOCK LOCK DOWN, then the CSM will set both the program and erase status register bits to indicate a command sequence error. Places the device into read status register mode. Reading the device will output the contents of the status register for the addressed bank. The device will automatically enter this mode for the addressed bank after a PROGRAM or ERASE operation has been initiated. Puts the device into the read protection configuration register mode so that reading the device will output the manufacturer/device codes, block lock status, protection register, or protection register lock. Puts the device into the read query mode so that reading the device will output common flash interface information. Suspends the currently executing PROGRAM/ERASE operation. The status register will indicate when the operation has been successfully suspended by setting either the program suspend (SR2) or erase suspend (SR6) and the WSM status bit (SR7) to a "1" (ready). The WSM will continue to idle in the suspend state, regardless of the state of all input control pins except RP#, which will immediately shut down the WSM and the remainder of the chip if RP# is driven to VIL. Writes a specific code into the device protection register. Locks the device protection register; data can no longer be changed. If the previous command was an ERASE SETUP command, then the CSM will close the address and data latches, and it will begin erasing the block indicated on the address pins. During programming/erase, the device will respond only to the READ STATUS REGISTER, PROGRAM/ERASE SUSPEND commands and will output status register data on the falling edge of OE# or CE#, whichever occurs last. If a program or erase operation was previously suspended, this command will resume the operation. During the read array mode, array data will be output on the data bus. If the previous command was PROTECTION CONFIGURATION SETUP, the CSM will latch the address and lock the block indicated on the address bus.
Alt. Program Setup Erase Setup
40h
Program Setup
First
50h
Clear Status Register
First
60h
Protection Configuration Setup
First
70h
Read Status Register
First
90h
Read Protection Configuration Register Read Query Program/Erase Suspend
First
98h B0h
First First
C0h
Program Device Protection Register Lock Device Protection Register
First First Second
D0h
Erase Confirm
Program/Erase Resume FFh 01h Read Array Lock Block
First First Second
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2 MEG x 16 1.8V ENHANCED+ BOOT BLOCK FLASH MEMORY
Table 5:
CODE 2Fh D0h
Command Descriptions (continued)
DEVICE MODE BUS CYCLE Second Second DESCRIPTION If the previous command was PROTECTION CONFIGURATION SETUP, the CSM will latch the address and lock down the block indicated on the address bus. If the previous command was PROTECTION CONFIGURATION SETUP, the CSM will latch the address and unlock the block indicated on the address bus. If the block had been previously set to lock down, this operation will have no effect. Unassigned command that should not be used.
Lock Down Unlock Block
00h
Invalid/Reserved
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2 MEG x 16 1.8V ENHANCED+ BOOT BLOCK FLASH MEMORY
Read Query
The read query mode outputs common flash interface (CFI) data when the device is read (see Table 12). Two bus cycles are required for this operation. It is possible to access the query by writing the read query command code 98h on DQ0-DQ7. Control signals CE# and OE# must be at a logic LOW level (VIL), and WE# and RP# must be at logic HIGH level (VIH) to read data from the query. The CFI data structure contains information such as block size, density, command set, and electrical specifications. To return to read array mode, write the read array command code FFh on DQ0-DQ7. During programming, VPP must remain in the appropriate VPP voltage range as shown in the Recommended Operating Conditions table.
ERASE OPERATIONS
An ERASE operation must be used to initialize all bits in an array block to "1". After BLOCK ERASE CONFIRM is issued, the CSM responds only to an ERASE SUSPEND command until the WSM completes its task. Block erasure inside the memory array sets all bits within the address block to logic "1". Erase is accomplished only by blocks; data at single address locations within the array cannot be erased individually. The block to be erased is selected by using any valid address within that block. Block erasure is initiated by a command sequence to the CSM: BLOCK ERASE SETUP (20h) followed by BLOCK ERASE CONFIRM (D0h) (see Figure 6). A two-command erase sequence protects against accidental erasure of memory contents. When the BLOCK ERASE CONFIRM command is complete, the WSM automatically executes a sequence of events to complete the block erasure. During this sequence, the block is programmed with logic "0", data is verified, all bits in the block are erased, and finally verification is performed to ensure that all bits are correctly erased. Monitoring the ERASE operation is possible through the status register (see the Status Register section). During the execution of an ERASE operation the ERASE SUSPEND command (B0h) can be entered to direct the WSM to suspend the ERASE operation. Once the WSM has reached the suspend state, it allows the CSM to respond only to the READ ARRAY, READ STATUS REGISTER, READ QUERY, READ CHIP PROTECTION CONFIGURATION, PROGRAM SETUP , PROGRAM/ERASE RESUME and LOCK SETUP (see the Block Locking section). During the ERASE SUSPEND operation, array data must be read from a block other than the one being erased. To resume the ERASE operation, an ERASE RESUME command (D0h) must be issued to cause the CSM to clear the suspend state previously set (see Figure 7). It is also possible that an ERASE can be suspended and a write to another block can be initiated. After the completion of a write, an erase can be resumed by writing an ERASE RESUME command.
Read Status Register
The status register is read by entering the command code 70h on DQ0-DQ7. Two bus cycles are required for this operation: one to enter the command code and a second to read the status register. In a READ cycle, the register data is updated on the falling edge of OE# or CE#, whichever occurs last.
PROGRAMMING OPERATIONS
There are two CSM commands for programming: PROGRAM SETUP and ALTERNATE PROGRAM SETUP (see Table 3). After the desired command code is entered (10h or 40h command code on DQ0-DQ7), the WSM takes over and correctly sequences the device to complete the PROGRAM operation. The WRITE operation may be monitored through the status register (see the Status Register section). During this time, the CSM will only respond to a PROGRAM SUSPEND command until the PROGRAM operation has been completed, after which time all commands to the CSM become valid again. The PROGRAM operation can be suspended by issuing a PROGRAM SUSPEND command (B0h). Once the WSM reaches the suspend state, it allows the CSM to respond only to READ ARRAY, READ STATUS REGISTER, READ PROTECTION CONFIGURATION, READ QUERY, and PROGRAM RESUME. During the PROGRAM SUSPEND operation, array data should be read from an address other than the one being programmed. To resume the PROGRAM operation, a PROGRAM RESUME command (D0h) must be issued to cause the CSM to clear the suspend state previously set (see Figure 4 for programming operation and Figure 5 for program suspend and program resume).
2 Meg x 16, 1.8V Enhanced+ Boot Block Flash Memory MT28F320A18_3.fm - Rev. 3, Pub. 9/2002
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2 MEG x 16 1.8V ENHANCED+ BOOT BLOCK FLASH MEMORY
Table 6: Command State Machine Current/Next States
COMMAND INPUT AND NEXT STATE DATA WHEN READ Array Status Config. CFI Status Status Status Status Array Read Array Program Suspend Read Array Program Suspend Read Array Program Suspend Read Array Program Suspend Read Array Read Configuration Program Suspend Read Configuration Program Suspend Read Configuration Program Suspend Read Configuration Program Suspend Read Configuration READ ARRAY FF Read Array Read Array Read Array Read Array Read Array READ CONFIG. 90 Read Configuration Read Configuration Read Configuration Read Configuration Read Configuration READ STATUS REG. 70 Read Status Read Status Read Status Read Status Read Status CLEAR STATUS REG. 50 Clear Status Clear Status Clear Status Clear Status Clear Status READ QUERY 98 Read Query Read Query Read Query Read Query Read Query ERASE SETUP 20 Erase Setup Erase Setup Erase Setup Erase Setup Erase Setup
CURRENT STATE Read Array Read Status Read Configuration Read Query Clear Status Program Setup Program (not done) Program (done) Program Suspend Read Array Program Suspend Read Status Program Suspend Read Configuration Program Suspend Read Query Erase Setup Erase (Not Done) Erase (Done) Erase Command Error Program Setup in Erase Suspend Erase Suspend Program (Not Done) Erase Suspend (Done)
SR7 1 1 1 1 0 1 0 1 1
Program Program Read Status Program Suspend Read Status Program Suspend Read Status Program Suspend Read Status Program Suspend Read Status Clear Status Program Suspend Clear Status Program Suspend Clear Status Program Suspend Clear Status Program Suspend Clear Status Read Query Program Suspend Read Query Program Suspend Read Query Program Suspend Read Query Program Suspend Read Query Erase Setup Program Suspend Read Array Program Suspend Read Array Program Suspend Read Array Program Suspend Read Array
1
Status
1
Config.
1
CFI
1 0 1 1 1 1 1
Status Status Status Status Status Status Status Erase Suspend Read Array Erase Suspend Read Array Erase Suspend Read Array Erase Suspend Read Array Erase Suspend Read Array Erase Suspend Read Configuration Erase Suspend Read Configuration Erase Suspend Read Configuration Erase Suspend Read Configuration Erase Suspend Read Configuration Erase Suspend Read Configuration Erase Suspend Read Configuration Read Array Read Array Read Configuration Read Configuration
Erase Command Error Erase Read Status Read Status Clear Status Clear Status Read Query Read Query Erase Setup Erase Setup
Program in Erase Suspend Program in Erase Suspend Erase Suspend Read Status Erase Suspend Read Status Erase Suspend Read Status Erase Suspend Read Status Erase Suspend Read Status Erase Suspend Clear Status Erase Suspend Clear Status Erase Suspend Clear Status Erase Suspend Clear Status Erase Suspend Clear Status Erase Suspend Read Query Erase Suspend Read Query Erase Suspend Read Query Erase Suspend Read Query Erase Suspend Read Query Erase Suspend Read Array Erase Suspend Read Array Erase Suspend Read Array Erase Suspend Read Array Erase Suspend Read Array
Erase Suspend Read Array
1
Array
Erase Suspend Read Status Erase Suspend Read Configuration Erase Suspend Read Query Erase Suspend Lock Setup Erase Suspend Lock
1
Status
1
Config.
1
CFI
1 1
Status Status Erase Suspend Read Array Erase Suspend Read Array
Erase Suspend Lock Error Erase Suspend Read Status Erase Suspend Read Status Erase Suspend Clear Status Erase Suspend Clear Status Erase Suspend Read Query Erase Suspend Read Query Erase Suspend Read Array Erase Suspend Read Array
Erase Suspend Lock Down
1
Status
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Table 6: Command State Machine Current/Next States (continued)
COMMAND INPUT AND NEXT STATE DATA WHEN READ Status READ ARRAY FF Erase Suspend Read Array Erase Suspend Read Array Erase Suspend Program Suspend Read Array Erase Suspend Program Suspend Read Array Erase Suspend Program Suspend Read Array Erase Suspend Program Suspend Read Array READ CONFIG. 90 Erase Suspend Read Configuration Erase Suspend Read Configuration Erase Suspend Program Suspend Read Configuration Erase Suspend Program Suspend Read Configuration Erase Suspend Program Suspend Read Configuration Erase Suspend Program Suspend Read Configuration READ STATUS REG. 70 Erase Suspend Read Status Erase Suspend Read Status Erase Suspend Program Suspend Read Status Erase Suspend Program Suspend Read Status Erase Suspend Program Suspend Read Status Erase Suspend Program Suspend Read Status CLEAR STATUS REG. 50 Erase Suspend Clear Status Erase Suspend Clear Status Erase Suspend Program Suspend Clear Status Erase Suspend Program Suspend Clear Status Erase Suspend Program Suspend Clear Status Erase Suspend Program Suspend Clear Status READ QUERY 98 Erase Suspend Read Query Erase Suspend Read Query Erase Suspend Program Suspend Read Query Erase Suspend Program Suspend Read Query Erase Suspend Program Suspend Read Query Erase Suspend Program Suspend Read Query ERASE SETUP 20 Erase Suspend Read Array Erase Suspend Read Array Erase Suspend Program Suspend Read Array Erase Suspend Program Suspend Read Array Erase Suspend Program Suspend Read Array Erase Suspend Program Suspend Read Array
CURRENT STATE Erase Suspend Unlock
SR7 1
Erase Suspend Lock Error
1
Status
Erase Suspend Program Suspend Read Array
1
Array
Erase Suspend Program Suspend Read Status
1
Status
Erase Suspend Program Suspend Read Configuration Erase Suspend Program Suspend Read Query
1
Config.
1
CFI
OTP Program Setup OTP Program (Not Done) OTP Program (Done) Lock Setup Lock Lock Down Unlock Lock Error
1 0 1 1 1 1 1 1
Status Status Status Status Status Status Status Status Read Array Read Array Read Array Read Array Read Configuration Read Configuration Read Configuration Read Configuration Read Array Read Configuration
OTP Program OTP Program Read Status Clear Status Read Query Erase Setup
Lock Error Read Status Read Status Read Status Read Status Clear Status Clear Status Clear Status Clear Status Read Query Read Query Read Query Read Query Erase Setup Erase Setup Erase Setup Erase Setup
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Table 6: Command State Machine Current/Next States (continued)
COMMAND INPUT AND NEXT TABLE PROGRAM/ ERASE RESUME, UNLOCK CURRENT STATE Read Array Read Status Read Configuration Read Query Clear Status Program Setup Program (not done) Program (done) Program Suspend Read Array Program Suspend Read Status Program Suspend Read Configuration Program Suspend Read Query Erase Setup Erase (Not Done) Erase (Done) Erase Command Error Program Setup in Erase Suspend Erase Suspend Program (Not Done) SR7 1 1 1 1 1 1 0 1 1 1 1 1 1 0 1 1 1 1 Program in Erase Suspend Read Array Read Array Program Setup Program Setup Program Read Array Program Program Program Program Erase Erase Suspend Read Status Read Array Read Array OTP Program Setup OTP Program Setup Lock Setup Lock Setup Program Setup Program Suspend Status Read Array OTP Program Setup D0 Read Array Read Array Read Array Read Array Read Array PROGRAM/ ERASE SUSPEND B0 Read Array Read Array Read Array Read Array Read Array OTP PROGRAM SETUP C0 OTP Program Setup OTP Program Setup OTP Program Setup OTP Program Setup OTP Program Setup Program Program Lock Setup Read Array
PROGRAM SETUP 10/40 Program Setup Program Setup Program Setup Program Setup Program Setup
LOCK SETUP 60 Lock Setup Lock Setup Lock Setup Lock Setup Lock Setup
LOCK 01
LOCK DOWN 2F Read Array Read Array Read Array Read Array Read Array
Program Suspend Read Array Program Suspend Read Array Program Suspend Read Array Program Suspend Read Array Erase Command Error Erase Read Array Read Array
Program in Erase Suspend Erase Suspend Program Suspend Read Status Erase Suspend Read Array Program in Erase Suspend
Erase Suspend (Done)
1
Erase
Program Setup in Erase Suspend Program Setup in Erase Suspend Program Setup in Erase Suspend Program Setup in Erase Suspend Program Setup in Erase Suspend
Erase Suspend Lock Setup Erase Suspend Lock Setup Erase Suspend Lock Setup Erase Suspend Lock Setup Erase Suspend Lock Setup
Erase Suspend Read Array
Erase Suspend Read Array
1
Erase
Erase Suspend Read Array
Erase Suspend Read Array
Erase Suspend Read Status Erase Suspend Read Configuration Erase Suspend Read Query Erase Suspend Lock Setup Erase Suspend Lock
1
Erase
Erase Suspend Read Array
Erase Suspend Read Array
1
Erase
Erase Suspend Read Array
Erase Suspend Read Array
1
Erase
Erase Suspend Read Array
Erase Suspend Read Array
1 1
Erase Suspend Unlock Erase Program Setup in Erase Suspend Program Setup in Erase Suspend
Erase Suspend Lock Error Erase Suspend Read Array Erase Suspend Lock Setup Erase Suspend Lock Setup
Erase Suspend Lock
Erase Suspend Lock Down
Erase Suspend Read Array
Erase Suspend Lock Down
1
Erase
Erase Suspend Read Array
Erase Suspend Read Array
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Table 6: Command State Machine Current/Next States (continued)
COMMAND INPUT AND NEXT TABLE PROGRAM/ ERASE RESUME, UNLOCK CURRENT STATE Erase Suspend Unlock SR7 1 D0 Erase PROGRAM/ ERASE SUSPEND B0 OTP PROGRAM SETUP C0
PROGRAM SETUP 10/40 Program Setup in Erase Suspend Program Setup in Erase Suspend
LOCK SETUP 60 Erase Suspend Lock Setup Erase Suspend Lock Setup
LOCK 01
LOCK DOWN 2F
Erase Suspend Read Array
Erase Suspend Read Array
Erase Suspend Lock Error
1
Erase
Erase Suspend Read Array
Erase Suspend Read Array
Erase Suspend Program Suspend Read Array Erase Suspend Program Suspend Read Status Erase Suspend Program Susp. Read Configuration Erase Suspend Program Suspend Read Query OTP Program Setup OTP Program (Not Done) OTP Program (Done) Lock Setup Lock Lock Down Unlock Lock Error
1 1 1 1 1 0 1 1 1 1 1 1
Erase Suspend Program Erase Suspend Program Erase Suspend Program Erase Suspend Program
Erase Suspend Program Suspend Read Array Erase Suspend Program Suspend Read Array Erase Suspend Program Suspend Read Array Erase Suspend Program Suspend Read Array
Read Array Unlock Read Array Read Array Read Array Read Array
Program Setup
Read Array
OTP Program Setup OTP Program Setup OTP Program Setup OTP Program Setup OTP Program Setup
Lock Setup Lock Lock Setup Lock Setup Lock Setup Lock Setup
Read Array Lock Down Read Array Read Array Read Array Read Array
Lock Error Program Setup Program Setup Program Setup Program Setup Read Array Read Array Read Array Read Array
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BLOCK LOCKING
The MT28F320A18 Flash memory provides a flexible locking scheme that allows each block to be individually locked or unlocked with no latency. The device offers two-level protection for the blocks. The first level allows software-only control of block locking (for data that needs to be changed frequently), while the second level requires hardware interaction before locking can be changed (code that does not require frequent updates). Control pins WP#, DQ1, and DQ0 define the state of a block; for example, state [001] means WP# = 0, DQ1 = 0 and DQ0 = 1. Table 9 defines all of the possible locking states. Note: All blocks are software-locked upon powerup sequence completion.
Locked Down State
Blocks that are locked down (state [011]) are protected from PROGRAM and ERASE operations, but their protection status cannot be changed using software commands alone. A locked or unlocked block can be locked down by writing the lock down command sequence, 60h followed by 2Fh. Locked down blocks revert to the locked state when the device is reset or powered down. The lock down function is dependent on the WP# input pin. When WP# = 0, blocks in lock down [011] are protected from program, erase and lock status changes. When WP# = 1, the lock down function is disabled ([111]) and locked down blocks can be individually unlocked by a software command to the [110] state, where they can be erased and programmed. These blocks can then be relocked [111] and unlocked [110] as desired as long as WP# remains HIGH. When WP# goes LOW, blocks that were previously locked down return to the locked down state [011] regardless of any changes made while WP# was HIGH. Device reset or power-down resets all locked blocks, including those in lock down, to locked state (see Table 9).
Locking operation
The following summarizes the locking operation. 1. All blocks are locked on power-up. They can then be unlocked or locked down with the UNLOCK and LOCK DOWN commands. 2. The LOCK DOWN command locks a block and prevents it from being unlocked when WP# = 0. * When WP# = 1, lock down is overridden. Commands can then unlock/lock locked down blocks. * When WP# returns to 0, locked down blocks return to lock down. * Lock down is cleared only when the device is reset or powered down.
Reading a Block's Lock Status
The lock status of every block can be read in the read device identification mode. To enter this mode, write 90h to the device. Subsequent READs at block address + 00002h will output the lock status of that block. The lowest two outputs, DQ0 and DQ1, represent the lock status. DQ0 indicates the block lock/ unlock status and is set by the LOCK command and cleared by the UNLOCK command. It is also automatically set when entering lock down. DQ1 indicates lock down status and is set by the LOCK DOWN command. It can only be cleared by reset or power-down, not by software. Table 9 shows the locking state transition scheme.
Locked State
After a power-up sequence completion, or after a reset sequence, all blocks are locked (states [001] or [101]). This means full protection from alteration. Any PROGRAM or ERASE operations attempted on a locked block will return an error on bit SR1 of the status register. The status of a locked block can be changed to unlocked or lock down using the appropriate software commands. Writing the lock command sequence, 60h followed by 01h, can lock an unlocked block.
Locking Operations during Erase Suspend
Changes to block lock status can be performed during an ERASE SUSPEND by using the standard locking command sequences to unlock, lock, or lock down. This is useful in the case when another block needs to be updated while an ERASE operation is in progress. To change block locking during an ERASE operation, first write the ERASE SUSPEND command (B0h), then check the status register until it indicates that the ERASE operation has been suspended. Next, write the desired lock command sequence to block lock, and the 17
(c)2002, Micron Technology Inc.
Unlocked State
Unlocked blocks (states [000], [100], [110]) can be programmed or erased. All unlocked blocks return to the locked state when the device is reset or powered down. An unlocked block can be locked or locked down using the appropriate software command sequence (see Table 4).
2 Meg x 16, 1.8V Enhanced+ Boot Block Flash Memory MT28F320A18_3.fm - Rev. 3, Pub. 9/2002
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lock status will be changed. After completing LOCK, READ or PROGRAM operations, resume the ERASE operation with the ERASE RESUME command (D0h). If a block is locked or locked down during a suspend erase of the same block, the locking status bits will change immediately. But, when resumed, the erase operation will complete. A locking operation cannot be performed during a PROGRAM SUSPEND. Following protection configuration setup (60h), an invalid command will produce a lock command error (SR4 and SR5 will be set to "1") in the status register. If a lock command error occurs during an ERASE SUSPEND, SR4 and SR5 will be set to "1" and will remain at "1" after the ERASE SUSPEND is resumed. When the ERASE is complete, any possible error during the ERASE cannot be detected via the status register because of the previous locking command error. A similar situation happens if an error occurs during a program operation error nested within an ERASE SUSPEND.
Status Register Error checking
Using nested locking or program command sequences during ERASE SUSPEND can introduce ambiguity into status register results.
Table 7:
MODE
Bus Operations
RP# VIH VIH VIH VIL VIH CE# VIL VIH VIL X VIL OE# VIL X VIH X VIH WE# VIH X X X VIL ADDRESS X X X X X DQ0-DQ15 DOUT High-Z High-Z High-Z DIN
Read (array, status registers, device identification register, or query) Standby Output Disable Reset Write
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Table 8:
WSMS 7 STATUS BIT # SR7
Status Register Bit Definition
ESS 6 ES 5 PS 4 VPPS 3 PSS 2 BLS 1 R 0
STATUS REGISTER BIT WRITE STATE MACHINE STATUS (WSMS) 1 = Ready 0 = Busy ERASE SUSPEND STATUS (ESS) 1 = BLOCK ERASE Suspended 0 = BLOCK ERASE in Progress/Completed ERASE STATUS (ES) 1 = Error in Block Erasure 0 = Successful BLOCK ERASE PROGRAM STATUS (PS) 1 = Error in PROGRAM 0 = Successful PROGRAM VPP STATUS (VPPS) 1 = VPP Low Detect, Operation Abort 0 = VPP = OK
DESCRIPTION Check write state machine bit first to determine word program or block erase completion, before checking program or erase status bits. When ERASE SUSPEND is issued, WSM halts execution and sets both WSMS and ESS bits to "1." ESS bit remains set to "1" until an ERASE RESUME command is issued. When this bit is set to "1," WSM has applied the maximum number of erase pulses to the block and is still unable to verify successful block erasure. When this bit is set to "1," WSM has attempted but failed to program a word. The VPP status bit does not provide continuous indication of the VPP level. The WSM interrogates the VPP level only after the program or erase command sequences have been entered. The WSM informs the system if VPP < 0.9V. The VPP level is also checked before the PROGRAM/ERASE operation is verified by the WSM. When PROGRAM SUSPEND is issued, WSM halts execution and sets both WSMS and PSS bits to "1." PSS bit remains set to "1" until a PROGRAM RESUME command is issued. If a PROGRAM or ERASE operation is attempted to one of the locked blocks, this is set by the WSM. The operation specified is aborted and the device is returned to read status mode.
SR6
SR5
SR4
SR3
SR2
SR1
SR0
PROGRAM SUSPEND STATUS (PSS) 1 = Program Suspended 0 = Program in Progress/Completed BLOCK LOCK STATUS (BLS) 1 = PROGRAM/ERASE Attempted on a Locked Block; Operation Aborted 0 = No operation to locked blocks RESERVED FOR FUTURE ENHANCEMENTS This bit is reserved for future enhancements.
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Figure 4: Automated Word Programming Flowchart
Start
BUS OPERATION COMMAND WRITE WRITE PROGRAM SETUP WRITE DATA
COMMENTS Data = 40h or 10h Addr = Address of word to be programmed Data = Word to be programmed Addr = Address of word to be programmed Status register data Toggle OE# or CE# to update status register. Check SR7 1 = Ready, 0 = Busy
Issue PROGRAM SETUP Command and Word Address
WRITE
Issue Word Address and Word Data
READ
Read Status Register Bits NO NO SR7 = 1? YES Full Status Register Check (optional)1 PROGRAM SUSPEND?
PROGRAM SUSPEND Loop
Standby
Repeat for subsequent words. Write FFh after the last word programming operation to return the device to read array mode.
YES
Word Program Completed FULL STATUS REGISTER CHECK FLOW Read Status Register Bits
BUS OPERATION COMMAND Standby Standby Standby
COMMENTS Check SR1 1 = Detect locked block Check SR3 1 = Detect VPP LOW Check SR43 1 = Word program error
SR1 = 0? YES
NO PROGRAM Attempted on a Locked Block
NO SR3 = 0? YES NO SR4 = 0? YES Word Program Passed
VPP Range Error
Word Program Failed
Notes: 1. Full status register check can be done after each word or after a sequence of words. 2. SR3 must be cleared before attempting additional PROGRAM/ERASE operations. 3. SR5 is cleared only by the CLEAR STATUS REGISTER command in cases where multiple blocks are erased before full status is checked.
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Figure 5: PROGRAM SUSPEND/ PROGRAM RESUME Flowchart
Start
BUS OPERATION COMMAND WRITE READ PROGRAM SUSPEND COMMENTS Data = B0h Status register data Toggle OE# or CE# to update status register. Check SR7 1 = Ready Check SR2 1 = Suspended Data = FFh Read data from block other than that being programmed. Data = D0h
Issue PROGRAM SUSPEND Command
Standby Standby
Read Status Register Bits
WRITE READ
READ MEMORY
NO SR7 = 1? YES NO SR2 = 1? YES Issue READ ARRAY Command PROGRAM Complete
WRITE
PROGRAM RESUME
Finished Reading ? YES Issue PROGRAM RESUME Command
NO
PROGRAM Resumed
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Figure 6: BLOCK ERASE Flowchart
Start Issue ERASE SETUP Command and Block Address
BUS OPERATION COMMAND WRITE WRITE ERASE SETUP
COMMENTS Data = 20h Block Addr = Address within block to be erased Data = D0h Block Addr = Address within block to be erased Status register data Toggle OE# or CE# to update status register. Check SR7 1 = Ready, 0 = Busy
WRITE
ERASE
Issue BLOCK ERASE CONFIRM Command and Block Address
READ
ERASE SUSPEND Loop NO NO
Read Status Register Bits
Standby
SR 7 = 1? YES Full Status Register Check (optional)1
ERASE SUSPEND?
YES
Repeat for subsequent blocks. Write FFh after the last BLOCK ERASE operation to return the device to read array mode.
BLOCK ERASE Completed FULL STATUS REGISTER CHECK FLOW Read Status Register Bits
BUS OPERATION COMMAND Standby
COMMENTS Check SR1 1 = Detect locked block Check SR32 1 = Detect Vpp block Check SR4 and SR5 1 = Block erase command error Check SR53 1 = Block erase error
NO SR1 = 0? YES NO SR3 = 0? YES NO SR5 = 0? YES BLOCK ERASE Passed
ERASE Attempted on a Locked Block
Standby Standby
VPP Range Error
Standby
BLOCK ERASE Failed
Notes: 1. Full status register check can be done after each block or after a sequence of blocks. 2. SR3 must be cleared before attempting additional PROGRAM/ERASE operations. 3. SR5 is cleared only by the CLEAR STATUS REGISTER command in cases where multiple blocks are erased before full status is checked.
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Figure 7: ERASE SUSPEND/ERASE RESUME Flowchart
Start
BUS OPERATION COMMAND Write READ ERASE SUSPEND
COMMENTS Data = B0h Status register data Toggle OE# or CE# to update status register. Check SR7 1 = Ready Check SR6 1 = Suspended Data = FFh Read data from block other than that being erased. Data = D0h
Issue ERASE SUSPEND Command
Standby Standby
Read Status Register Bits
WRITE READ
READ MEMORY
NO SR7 = 1? YES NO SR6 = 1? YES ERASE Complete PROGRAM
WRITE
ERASE RESUME
READ or PROGRAM? READ Issue READ ARRAY Command
PROGRAM Loop
(Note 1)
NO
READ or PROGRAM Complete? YES Issue ERASE RESUME Command
ERASE Continued2
Notes: 1. See Word Programming Flowchart for complete programming procedure. 2. See BLOCK ERASE Flowchart for complete erasure procedure.
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Table 9:
WP# 0 0 0 1 1 1 1 0
Block Locking State Transition
DQ1 0 0 1 0 0 1 1 1 DQ0 0 1 1 0 1 0 1 0 NAME Unlocked Locked (Default) Lock down Unlocked Locked Lock down disabled Lock down disabled Invalid ERASE/ PROGRAM ALLOWED Yes No No Yes No Yes No No LOCK To [001] No Change No Change To [101] No Change To [111] No Change No Change UNLOCK No Change To [000] No Change No Change To [100] No Change To [110] No Change LOCK DOWN To [011] To [011] No Change To [111] To [111] To [111] No Change No Change
Table 10: Chip Configuration Addressing1
ITEM Manufacturer Code (x16) Device Code Top boot configuration Bottom boot configuration Block Lock Configuration Block is unlocked Block is locked Block is locked down Chip Protection Register Lock Chip Protection Register 1 Chip Protection Register 2 ADDRESS2 000000h 000001h DATA 002Ch 32Mb 00C2h 00C3h Lock DQ0 = 0 DQ0 = 1 DQ1 = 1 PR-Lock DQ1 = 0 locked DQ1 = 1 unlocked Factory Data User Data
BA + 000002h
80h
81h-84h 85h-88h
Notes: 1. Other locations within the configuration address space are reserved by Micron for future use. 2. "XX" specifies the block address of lock configuration.
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CHIP PROTECTION REGISTER
A 128-bit protection register can be used to fulfill the security considerations in the system (preventing the device substitution). The 128-bit security area is divided into two 64-bit segments. The first 64 bits are programmed at the manufacturing site with a unique 64-bit unchangeable number. The other segment is left blank for customers to program as desired. (See Figure 8). result in a status register error (program error bit SR4 and lock error bit SR1 = 1)
Locking the Chip Protection Register
The customer-programmable segment of the protection register can be locked by programming bit 1 of the PR lock location to "0". Bit 0 of this location is programmed to a "0" at the Micron factory to protect the unique device number. Bit 1 is set using the PROTECTION PROGRAM command to program FFFDh to the PR lock location. After these bits have been programmed, no further changes can be made to the values stored in the protection register. PROTECTION PROGRAM commands to a locked section will result in a status register error program error bit SR4 and lock error bit SR1 will be set to 1. Protection register lockout is not reversible.
Figure 8: Protection Register Memory Map
88h
85h 84h
4 Words User-Programmed 4 Words Factory-Programmed
VPP/VCC Program and Erase Voltages
The MT28F320A18 Flash memory provides in-system programming and erase with VPP in the 0.9V- 1.95V (VPP1) range. The 12V VPP (VPP2) mode programming is offered for compatibility with existing programming equipment. The fast programming algorithm is enabled at VPP = VPP2. The device can withstand 100,000 WRITE/ERASE operations when VPP = VPP1 or 100 WRITE/ERASE operations and 10 cumulative hours when VPP = VPP2. In addition to the flexible block locking, the VPP programming voltage can be held LOW for absolute hardware write protection of all blocks in the Flash device. When VPP is below VPPLK, any PROGRAM or ERASE operation will result in an error, prompting the corresponding status register bit (SR3) to be set. During WRITE and ERASE operations, the WSM monitors the VPP voltage level. WRITE/ERASE operations are allowed only when VPP is within the range specified in TABLE 11. When VCC is below VLKO or below VPPLK, any WRITE/ERASE operation will be disabled.
81h 80h
PR Lock
0
Reading the Chip Protection Register
The chip protection register is read in the device identification mode, loading the 90h command to the bank containing address 00h. Once in this mode, READ cycles from addresses shown in Table 10 retrieve the specified information. To return to the read array mode, write the READ ARRAY command (FFh).
Programming the Chip Protection Register
Executing the PROTECTION PROGRAM command enables the customer to program the user portion of the protection register. First, write the PROTECTION PROGRAM SETUP command, C0h; then write address and data to program. Attempts should not be made to address PROTECTION PROGRAM commands outside the defined protection register address space. Attempting to program to a previously locked protection register segment will
Table 11: VPP Range (V)
MIN In-System (VPP1) In-Factory (VPP2) 0.9 11.4 MAX 1.95 12.6
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READ CYCLE
Addresses can be accessed in a random order with an access time given by tAA = 70ns. When CE# and OE# are LOW, the data is placed on the data bus and the processor can read the data. switches to the automatic power saving mode. When the device switches to this mode, ICC is reduced to ICC2. The low level of power is maintained until another operation is initiated. In this mode, the I/O pins retain the data from the last memory address read until a new address is initiated. This mode is entered automatically if no address or control signal toggles.
STANDBY MODE
ICC supply current is reduced by applying a logic HIGH level on CE# and RP# to enter the standby mode. In the standby mode, the outputs are placed in High-Z. Applying a CMOS logic HIGH level on CE# and RP# reduces the current to ICC2 (MAX). If the device is deselected during an ERASE operation or during programming, the device continues to draw current until the operation is complete.
POWER-UP SEQUENCE
The following power-up sequence is recommended to properly initialize internal chip operations: * At power-up, RST# should be kept at VIL for 2S after VCC reaches VCC (MIN). * VccQ should not come up before Vcc. * VPP should be kept at VIL to maximize data integrity. When the power-up sequence is completed, RST# should be brought to VIH. To ensure proper power-up, the rise time of RST# (10%-90%) should be < 10S.
AUTOMATIC POWER SAVE MODE (APS)
Substantial power savings are realized during periods when the array is not being read and the device is in the active mode. During this time, the device
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ABSOLUTE MAXIMUM RATINGS*
Voltage to Any Ball Except Vcc and Vpp with Respect to Vss ............................. -0.5V to +2.45V Vpp Voltage (for BLOCK ERASE and PROGRAM with Respect to Vss) ........ -0.5V to +13.5V Vcc and VccQ Supply Voltage with Respect to Vss ............................. -0.3V to +2.45V Output Short Circuit Current ...............................100mA Operating Temperature Range ................-40C to +85C Storage Temperature Range ..................-55C to +125C Soldering Cycle ........................................... 260C for 10s *Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
RECOMMENDED OPERATING CONDITIONS
PARAMETER/CONDITION Operating temperature VCC supply voltage I/O supply voltage (VCC = 1.65V-1.95V) Supply voltage, when used as logic control VPP in-factory programming voltage Block erase cycling SYMBOL A VCC VCCQ1 VPP1 VPP2 VPP1 VPP2
t
MIN -40 1.65 1.65 0.9 11.4 100,000 -
MAX +85 1.95 1.95 1.95 12.6 - 100
UNITS C V V V V Cycles Cycles
o
NOTES
VPP = VPP1 VPP = VPP2
1
Notes: 1. VPP = VPP2 is a maximum of 10 cumulative hours.
Figure 9: AC Input/Output Reference Waveform
VCC Input VSS VCC/2 Test Points VCCQ/2 Output
AC test inputs are driven at VCC for a logic 1 and VSS for a logic 0. Input timing begins at VCC/2, and output timing ends at VCCQ/2. Input rise and fall times (10% to 90%) < 5ns.
Figure 10: Output Load Circuit
VCC 14.5K I/O 14.5K VSS 30pF
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DC CHARACTERISTICS
VCC = 1.65V-1.95V VCCQ = 1.65V-1.95V PARAMETER Input Low Voltage Input High Voltage Output Low Voltage IOL = 100A Output High Voltage IOH = 100A VPP Lock Out Voltage VPP During Program/Erase Operations VCC Program/Erase Lock Voltage Input Leakage Current Output Leakage Current VCC Read Current VCC Standby Current1 Program Current VPP = VPP1 VPP = VPP2 Erase Current VPP = VPP1 VPP = VPP2 VCC Erase Suspend Current VPP = VPP1 VCC Program Suspend Current VPP = VPP1 VPP Read Current VPP VCC VPP Standby Current VPP = VPP1 VPP Erase Suspend Current VPP = VPP1 VPP Program Suspend Current VPP = VPP1 Notes: 1. RP# = VIH or VIL. SYMBOL VIL VIH VOL VOH VPPLK VPP1 VPP2 VLKO IL IOZ ICC1 ICC2 ICC3 - - ICC4 - - ICC5 - ICC6 - IPP1 - IPP2 - IPP5 - IPP6 - 0.5 5 0.5 5 A A 0.5 5 A 0.5 15 5 50 A A 5 50 A 25 25 40 40 mA mA 25 12 40 40 mA mA MIN -0.2 VCCQ - 0.2 - VCCQ - 0.1 - 0.9 11.4 1 -1 -1 - - TYP - - - - - - - - - - 9 15 MAX 0.2 VCCQ + 0.2 0.1 - 0.4 1.95 12.6 - 1 1 18 50 UNIT V V V V V V V V A A mA A
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READ CYCLE TIMING REQUIREMENTS1
-70 VCC = 1.65V-1.95V PARAMETER Address to output delay CE# LOW to output delay OE# LOW to output delay RP# HIGH to output delay CE# or OE# HIGH to output High-Z Output hold from address, CE#, or OE# change READ cycle time SYMBOL
t t t t
MIN
MAX 70 70 20 150 15
UNITS ns ns ns ns ns ns ns
AA
ACE
AOE OD OH RC 0 70
RWH
t t
t
Notes: 1. See Figures 11 and 12 for timing requirements and output load configuration.
WRITE CYCLE TIMING REQUIREMENTS
-70 VCC = 1.65V-1.95V PARAMETER RP# HIGH recovery to WE# going LOW CE# setup to WE# going LOW Write pulse width Data setup to WE# going HIGH Address setup to WE# going HIGH CE# hold from WE# HIGH Data hold from WE# HIGH Address hold from WE# HIGH Write pulse width HIGH RP# pulse width WP# setup to WE# going HIGH VPP setup to WE# going HIGH Write recovery before READ WP# hold from valid SRD VPP hold from valid SRD WE# HIGH to data valid
t t
SYMBOL
t t t
MIN 150 0 70 70 70 0 0 0 30 100 200 200 50 0 0
t
MAX
UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
RS CS
WP DS AS
t t t t t
CH
DH AH RP
WPH
t
RHS VPS
t t
WOS RHH WB
t t
VPPH
t
AA+50
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ERASE AND PROGRAM CYCLE TIMING REQUIREMENTS
VPP = 1.65V-1.95V VCC = 1.65V-1.95V PARAMETER 4KW block program time 32KW block program time Word program time 4KW block erase time 32KW block erase time Program suspend latency Erase suspend latency
t t t
VPP = 12V 5% VCC = 1.65V-1.95V TYP MAX UNITS s s 5 0.03 0.3 130 2.5 4 s s s s s
SYMBOL
t t
TYP 0.1 0.8 8 0.3 1 2.5 2.5
MAX 0.3 2.4 150 2.5 4 5 5
BWPB
t t t
BWMB
WHQV1/ EHQV1 WHQV2/ EHQV2 WHQV3/ EHQV3 WHRH1/tEHRH1 WHRH2/tEHRH2
t t
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Two-Cycle Programming/ERASE Operation
A0-A20 VIH VALID ADDRESS VIL VIH CE# VIL
tCS tCH tWOS
VALID ADDRESS
tAS tAH
VALID ADDRESS
VIH OE# VIL VIH WE# VIL VOH DQ0-DQ15 VOL High-Z
tRS tDH tRHS tWP tWB tWPH
CMD
CMD/ DATA
tDS
STATUS
VIH RP# VIL VIH WP# VIL
tRHH
tVPS
tVPPH
VIPPH VIPPLK VPP VIL
UNDEFINED
WRITE TIMING PARAMETERS
-70 VCC = 1.65V-1.95V SYMBOL
tRS t t t t
-70 VCC = 1.65V-1.95V UNITS ns ns ns ns ns ns ns ns SYMBOL
tWPH t t t t
MIN 150 0 70 70 70 0 0 0
MAX
MIN 30 200 200 50 0 0
MAX
UNITS ns ns ns ns ns ns
CS WP DS AS
RHS VPS WOS RHH
tCH t
tVPPH t
DH
WB
tAA+50
ns
tAH
Notes: 1. The WRITE cycles for the WORD PROGRAMMING command are followed by a READ ARRAY DATA cycle.
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Single Asynchronous READ Operation
A0-A20 VIH VALID ADDRESS VIL
tRC tAA tOD
VIH CE# VIL
tACE
VIH OE# VIL
tOH
VIH WE# VIL VOH DQ0-DQ15 VOL High-Z
tRWH tAOE
VALID OUTPUT
RP#
VIH VIL
UNDEFINED
READ TIMING PARAMETERS
-70 VCC = 1.65V-1.95V SYMBOL
tAA t t t
-70 VCC = 1.65V-1.95V UNITS ns ns ns ns SYMBOL
tRC t t
MIN
MAX 70 70 20 150
MIN
MAX 70 15
UNITS ns ns ns
ACE AOE RWH
OD OH 0
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Reset Operation
CE# VIH VIL RP# VIH VIL
tRP
OE#
VIH VIL
DQ0-DQ15
VOH VOL
tRWH
READ AND WRITE TIMING PARAMETERS
-70 VCC = 1.65V-1.95V SYMBOL
t
MIN
MAX 150
UNITS ns ns
RWH 100
tRP
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Table 12: CFI
OFFSET 00 01 03 - 0F 10, 11 12 13, 14 15, 16 17, 18 19, 1A 1B 1C 1D 1E 1F 20 21 22 23 24 25 26 27 28 29 2A, 2B 2C 2D, 2E 2F, 30 31, 32 33, 34 35, 36 37 38 39 3A 3B 3C 3D DATA 2Ch C2h/C3h reserved 0051, 0052 0059 0003, 0000 0035, 0000 0000, 0000 0000, 0000 0017 0019 00B4 00C6 0003 0000 0009 0000 000C 0000 000C 0000 0016 DESCRIPTION Manufacturer Code 32Mb Top /Bottom Boot Block Device Code Reserved "QR" "Y" Primary OEM Command Set Address for Primary Extended Table Alternate OEM Command Set Address for OEM Extended Table VCC MIN for Erase/Write; Bit7-Bit4 Volts in BCD; Bit3-Bit0 100mV in BCD VCC MAX for Erase/Write; Bit7-Bit4 Volts in BCD; Bit3-Bit0 100mV in BCD VPP MIN for Erase/Write; Bit7-Bit4 Volts in Hex; Bit3-Bit0 100mV in BCD, 0000 = VPP input VPP MAX for Erase/Write; Bit7-Bit4 Volts in Hex; Bit3-Bit0 100mV in BCD, 0000 = VPP input Typical timeout for single byte/word program, 2n s, 0000 = not supported Typical timeout for maximum size multiple byte/word program, 2n s, 0000 = not supported Typical timeout for individual block erase, 2n ms, 0000 = not supported Typical timeout for full chip erase, 2n ms, 0000 = not supported Maximum timeout for single byte/word program, 2n s, 0000 = not supported Maximum timeout for maximum size multiple byte/word program, 2n s, 0000 = not supported Maximum timeout for individual block erase, 2n ms, 0000 = not supported Maximum timeout for full chip erase, 2n ms, 0000 = not supported Device size, 2n bytes; 0016 for 32Mb Bus Interface x8 = 0, x16 = 1, x8/x16 = 2 Flash device interface description 0000 = async
0001 0000 0000, 0000 Maximum number of bytes in multi-byte program or page, 2n 0002 Number of erase block regions within device (4K words and 32K words) 0007, 0000 Erase block region information 1, 8 blocks ... 0020, 0000 ...of 8KB 001E, 0000 63 = 3Eh for 32Mb 0000, 0001 ...64KB 0050, 0052 "PR" 0049 "I" 0030 Major Version number ASCII 0031 Minor version number, ASCII 0066 Optional Feature and Command Support 0000 Bit 0 Chip erase supported no = 0 0000 Bit 1 Suspend erase supported = yes = 1 0000 Bit 2 Suspend program supported = yes = 1 Bit 3 Chip lock/unlock supported = no = 0 Bit 4 Queued erase supported = no = 0 Bit 5 Instant individual block locking supported = yes = 1 Bit 6 Protection bits supported = yes = 1 Bit 7 Page mode read supported = no = 0 Bit 8 Synchronous read supported = no = 0 Bit 9 Simultaneous operation supported = no = 0
(c)2002, Micron Technology Inc.
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Table 12: CFI (continued)
OFFSET 3E 3F, 40 41 42 43 44, 45 46, 47 48 DATA DESCRIPTION 0001 Program supported after erase suspend = yes 0003, 0000 Bit 0 block lock status active = yes Bit 1 block lock down active = yes 0018 VCC supply optimum, 00 = not supported, Bit7-Bit4 Volts in BCD; Bit3-Bit0 100mV in BCD 00C0 VPP supply optimum, 00 = not supported, Bit7-Bit4 Volts in BCD; Bit3-Bit0 100mV in BCD 0001 Number of protection register fields in JEDEC ID space 0080, 0000 Lock bytes LOW address, lock bytes HIGH address 0003, 0003 2n factory programmed bytes, 2n user programmable bytes 0000 Background Operation 0000 = Not used 0001 = 4% block split 0002 = 12% block split 0003 = 25% block split 00004 = 50% block split Burst Mode Type 0000 = No burst mode 00x1 = 4 words max 00x2 = 8 words max 00x13 = 16 words max 001x = Linear burst, and/or 002x = Interleaved burst, and/or 004x = Continuous burst Page Mode Type 0000 = No page mode 0001 = 4-word page 0002 = 8-word page 0003 = 16-word page 0004 = 32-word page Not used
49
0000
4A
0000
4B
0000
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48-BALL FBGA
0.80 0.075
0.10 C
C
5.25 0.75 TYP BALL A1
SOLDER BALL MATERIAL: EUTECTIC 63% Sn, 37% Pb or 62% Sn, 36% Pb, 2% Ag SOLDER BALL PAD: O .27mm SUBSTRATE: PLASTIC LAMINATE MOLD COMPOUND: EPOXY NOVOLAC BALL A1 ID BALL #1 ID
46X O .35 SOLDER BALL DIAMETER REFERS TO POST REFLOW CONDITION. THE PRE-REFLOW DIAMETER IS O 0.33mm.
3.25 0.05 BALL A8 6.50 0.10 1.88 0.05
0.75 TYP C L 3.75
C L 2.625 0.05 3.50 0.05 7.00 0.10 1.20 MAX
Notes: 1. All dimensions in millimeters. 2. Package width and length do not include mold protrusion; allowable mold protrusion is 0.27mm per side. 3. Micron recommends a one-to-one ratio between the solder ball pad and the PCB. For more information, see Micron Technical Note, TN-00-11, "SMT Recommendations for BGA Assembly."
DATA SHEET DESIGNATIONS
Preliminary This data sheet contains initial characterization limits that are subject to change upon full characterization of production devices.
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REVISION HISTORY
Rev. 3, PRELIMINARY......................................................................................................................................................9/02 * Updated Status Register section * Updated Clear Status Register section * Updated Read Array section * Updated descriptions for command codes 20h, 70h, and D0h * Updated Read Status Register section * Removed tCBPH specification * Removed 16Mb information Rev. 2, ADVANCE .............................................................................................................................................................2/02 * Added reset pulse width information Original document, Rev. 1, Advance ............................................................................................................................10/01
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992 Micron and the M logo are registered trademarks and the Micron logo is a trademark of Micron Technology, Inc.
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(c)2002, Micron Technology Inc.

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